REMU: An FPGA-based Open-source Replayable EMUlator for System-level Evaluating and Debugging Processors
Event Time: 19th October, 2025, 13:00-17:00 (GMT-3)
Event Location: Lotte Hotel Seoul, Seoul, Korea
Organizers
Ke Zhang is a Professor at ICT of CAS. His research interests lie in heterogeneous computing in cloud and datacenters, as well as FPGA-based emulation for system-level evaluation and debugging within the FPGA cloud. He has built a self-contained FPGA cloud platform and provided publicly available cloud services for computer-system-related research and course labs.
Yazhou Wang, Si Zhang and Shiqi Liu are research engineers at ICT of CAS. Their research interests focus on FPGA infrastructure, security, and cloud-native computing, with contributions towards advancing the REMU framework.
Guanghui Hu and Panyu Wang are pursuing their master's degree at CAS. They focus on REMU optimizations aiming to support scalable system debugging on multi-FPGA.
Overview
We're running a hands-on half-day tutorial on REMU at MICRO 2025!
Tired of getting bogged down by the snail-paced logical simulation during system-level debugging and performance evaluation?
Say goodbye to the grind with our solution, REMU!
With its remarkable capability to rapidly emulate 23 billion cycles in just 79 seconds, along with offering fully bit-accurate and cycle-accurate visibility, REMU provides a better balance in efficiency and precision.
Join this tutorial and delve into a hands-on experience, where you can learn how to set up and customize the REMU framework with various instances of representative open-source RISC-V processors (e.g., classical Rocket chip in-order core and tailored XiangShan out-of-order core).
What is REMU?
REMU is an open-source academic FPGA-based emulation framework enabling cost-effective hardware checkpointing and deterministic replay to acquire fully bit-accurate and cycle-accurate visibility of target processors as well as system components (i.e., memory and peripherals). Details of REMU can be found in our ICCD'23 full paper.
Tutorial Schedule
| Time (GMT-3) | Topic |
|---|---|
| 13:00-13:30 | Overview of FPGA accelerated emulation |
| 13:30-14:00 | Introduction to REMU |
| 14:00-14:20 | Coffee Break |
| 14:20-15:00 | Hands-on system-level performance evaluation |
| 15:00-16:00 | Hands-on inspection and debugging of a complicated system |
| 16:00-17:00 | Summary and discussion |
Attendee Logistics/Requirements
We will provide publicly available cloud FPGA services for attendees to deploy REMU for system-level emulation. To follow along with the tutorial on the cloud FPGA services we provide, attendees will need to bring a laptop.
Either academic scholarship or industrial experts who are interested in the micro-architecture of processor chips, system architecture design, HW-SW co-design, etc., are welcome to participate in our tutorial.
Registration
To attend the tutorial, you need register for our in advance, so we can provide sufficient FPGA resources for attendees.
Contact us
For any further question, please contact huguanghui@ict.ac.cn or liushiqi@ict.ac.cn.
Screen Recording
We have placed the screen recording link here. If you are interested, you can click to view it.